Clock generating digital data receiver

Details Clock generating digital data receiver Clock generating digital data receiver

H - Electricity

04

L

340/165, 340/205

H04L 7/00 (2006.01) G11B 20/14 (2006.01) H03K 5/135 (2006.01)

Patent

CA 1171934

44-267/PRC1.11 CLOCK GENERATING DIGITAL DATA RECEIVER Abstract of the Invention The method and apparatus for implementation of a digital coherent receiver that can generate a synchronized clock signal from a random digital NRZ data stream having a certain amount of distortion and jitter, but a fixed bit rate. A block diagram is provided and its modes of operation are illustrated by sample timing diagrams. Its unique features and advantages are also presented in the context of other commonly known techniques and implementions such as the Universal Asynchronous Receiver/ Transmitter, and the Phase-Locked-Loop in similar applications.

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