Clock jitter suppressing circuit

Details Clock jitter suppressing circuit Clock jitter suppressing circuit

H - Electricity

04

B

340/72

H04B 15/00 (2006.01) H03K 5/135 (2006.01) H03K 5/156 (2006.01) H04L 7/027 (2006.01) H04L 7/033 (2006.01) H04L 7/00 (2006.01) H04L 7/04 (2006.01)

Patent

CA 2025660

Abstract of the Disclosure A clock jitter suppressing circuit includes a control circuit, a delay circuit, and a selection circuit. The delay circuit sequentially delays a clock signal at time intervals sufficiently shorter than the period of the clock signal. The selection circuit selects and outputs one of delay outputs from the delay circuit which is determined in accordance with a selection signal. The control circuit generates a selection signal for selecting a predetermined delay output when no jitter is caused in the clock signal. Every time jitter is caused in the clock signal, the control circuit generates a selection signal for selecting a delay output which is shifted by an amount corresponding to the phase amount of the jitter in a direction to cancel a polarity of the jitter.

Affiliated with

Also associated with

Rating

Clock jitter suppressing circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock jitter suppressing circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock jitter suppressing circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1877557