Clock level shifting circuit

Details Clock level shifting circuit Clock level shifting circuit

H - Electricity

03

F

330/20

H03F 3/45 (2006.01) H03K 5/02 (2006.01) H03K 19/018 (2006.01)

Patent

CA 1123923

DAGUE, G. I. 1-1 - 11 - CLOCK LEVEL SHIFTING CIRCUIT Abstract of the Disclosure A level shifting circuit for binary signals comprises a pair of equal value resistors connecting a common input signal to a pair of input terminals of a differential amplifier. A capacitor from one input terminal to ground stores the long term average input signal level for comparison with the instantaneous input signal level on the other input terminal. In another embodiment the range of input signal levels is modified by connecting equal value resistors from the input terminals to a voltage source. The invention provides amplification with minimum propagation delay, symmetrical propagation delay, a conventional logic level output signal and only requires a single power supply source for the amplifier circuit over a large range of input signal levels.

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