Clock phase alignment

Details Clock phase alignment Clock phase alignment

H - Electricity

04

L

H04L 7/02 (2006.01) H03L 7/08 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2096628

A phase error integrator (11) for determining the phase er- ror between a data signal and a clock signal frequency locked to the data signal has a data input and a clock input. In one em- bodiment the phase error integrator (11) is formed as two func- tional components, namely a phase error detector (20) and an in- tegrator chain (21). The phase error detector (20) sends to the integrator (21) one of two output signals (NAR, NAL) depend- ing on whether the phase error is positive or negative. The inte- grator chain has a number of outputs (ERR0-ERR13) the first half of which initially have a binary 1 and the second half of which initially have a binary 0. Depending on which output sig- nal arrives from the phase error detector the binary 1's shift right or the binary 0's shift left. The integrator may be combined with a delay block (15) connected to the outputs of the integrator chain (21). The data signal is fed to the delay block (15) and a delayed data output signal is obtained which is connected to the data input of the phase error integrator (11). The delay block (15) delays the data signal until there is concordance between the phase of the clock and delayed data signals.

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