Clock pulse regenerator

Details Clock pulse regenerator Clock pulse regenerator

H - Electricity

04

J

328/82

H04J 3/06 (2006.01) H04L 7/02 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1115356

Abstract of the Disclosure In a clock pulse regenerator for generating a clock pulse sequence in response to an incoming digital data signal, there is described a regen- erator which produces the clock pulse sequence substantially free from phase jitter and phase deviation. From an input digital data, an oscillator pro- duces a sequence of first pulses at a frequency greater than that of the input signal. In response to the first pulses, a first counter generates a sequence of regenerated clock pulses. The input digital signal and the regenerated clock pulses are gated to form a gate pulse having a pulse width proportional to the phase difference between the two signals. The gate pulse is selectively transmitted through a first gate and is then counted by a second counter which generates a pulse for every predetermined number of first pulses. Similarly, a third counter generates a pulse for each pre- determined number of leading and trailing edges of counted from the incoming data signal. The first pulses and second counter outputs are selectively transmitted through a second gate in response to the output pulses of the third counter. The outputs of the second gate are counted by a fourth counter which generates a further pulse for each predetermined number of inputs. These pulses are used to reset all four counters in readiness for the next data signal.

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