Clock recovery for serial data communications system

Details Clock recovery for serial data communications system Clock recovery for serial data communications system

G - Physics

06

F

354/231

G06F 1/06 (2006.01) G06F 1/04 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2019990

CLOCK RECOVERY FOR SERIAL DATA COMMUNICATIONS SYSTEM ABSTRACT OF THE DISCLOSURE In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage- controlled oscillator in response to the difference in phase between the incoming data signal and the clock oscillator output. A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output. A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to seek an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal. The control circuitry includes a counter for counting transitions of the clock to inhibit another detect operation from starting until three transitions after one has begun.

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