Clock recovery phase locked loop control using clock...

Details Clock recovery phase locked loop control using clock... Clock recovery phase locked loop control using clock...

H - Electricity

04

L

H04L 7/027 (2006.01) H03L 7/087 (2006.01) H03L 7/14 (2006.01) H03L 7/183 (2006.01) H04L 7/033 (2006.01) H03L 7/089 (2006.01) H03L 7/095 (2006.01) H04L 7/00 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2150860

A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) is comprised of providing a sequence of data pulses and a sequence of reference clock pulses, resetting the phase locked loop to force the VCO to its lowest operating frequency, releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, detecting the presence of data pulse transitions, in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, the outputting output clock pulses from the phase locked loop.

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