Clock regenerator

Details Clock regenerator Clock regenerator

H - Electricity

03

L

328/28, 328/87

H03L 7/00 (2006.01) H03L 7/099 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1262174

ABSTRACT OF THE DISCLOSURE A clock regenerator is designed as a phase locked loop (PLL) and comprises a phase detector (DET) which compares the phase of the input signal (Sp) with that of the output signal (Sa), the frequency of the phase detector being approximately N times smaller than the oscillator frequency. In the phase detector (DET), there are obtained from a regenerated output signal (Sa) two signals delayed by L/N periods, wherein L is a small integer, in order to form therefrom a pulse window comprising at least three zones. The clock regenerator comprises a loop filter (FIL) with a counter, the status of which is recorded in a logic circuit which controls a programmable divisor (DIV) in such a way that when the edges of the input pulse (Sp) fall in the central most zone, the counter counts toward zero and no correction is brought about.

510974

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