Clock signal generation system

Details Clock signal generation system Clock signal generation system

H - Electricity

04

N

350/88

H04N 5/93 (2006.01) H03L 7/183 (2006.01) H04N 5/12 (2006.01) H04N 5/932 (2006.01) H04N 9/804 (2006.01)

Patent

CA 1260607

Abstract of the Disclosure A television receiver includes a phase locked loop (PLL) which generates a clock signal having a frequency of N times the line frequency and being phase-locked to the horizontal line synchronizing signal. The clock signal produced by this PLL has a frequency which tends to jitter between N+1 and N-1 times the line frequency. To compensate for this jittering in the frequency of the clock signal, phase alignment circuitry is coupled to the PLL to align the phase of the clock signal to the horizontal drive signal produced by the PLL on the occurrence of each horizontal drive pulse. The PLL may also include a delay element which delays the horizontal drive signal applied to the phase comparator of the PLL. This delay element effectively advances the phase of the horizontal drive signal and the line-locked clock signal with respect to the horizontal sync signal to compensate for signal processing delays imparted in the generation of the horizontal drive signal and the clock signal.

571411

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