Clock skew avoidance technique for pipeline processors

Details Clock skew avoidance technique for pipeline processors Clock skew avoidance technique for pipeline processors

G - Physics

06

F

354/231

G06F 9/38 (2006.01) G06F 1/10 (2006.01)

Patent

CA 1302585

Abstract of the Disclosure A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

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