Clocked igfet logic circuit

Details Clocked igfet logic circuit Clocked igfet logic circuit

H - Electricity

03

K

328/128

H03K 19/00 (2006.01) H03K 19/017 (2006.01) H03K 19/096 (2006.01)

Patent

CA 1166321

- 12 - CLOCKED IGFET LOGIC CIRCUIT Abstract A clocked IGFET serial decoder circuit has a precharge transistor with its conduction channel connected between a VDD supply and an output terminal, a string of transistors with their conduction channels connected in series between the output terminal and a switch ground node and a ground switch transistor with its conduction channel connected between the switch ground node and a VSS supply. The gates of the transistors of the string receive input signals from clocked input buffers which bias the gates at VDD during the precharge interval when the precharge transistor is ON and the ground switch transistor is OFF. This allows the parasitic capacitances at the junctures of the transistors in the string to become substantially charged during the precharge interval and thus prevent rapid charge sharing at the output terminal when the circuit is enabled.

382029

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