Clocked logic circuit

Details Clocked logic circuit Clocked logic circuit

H - Electricity

03

K

328/128

H03K 19/096 (2006.01)

Patent

CA 1162993

- 11 - CLOCKED LOGIC CIRCUIT Abstract of the Disclosure A clocked IGFET logic circuit comprises a precharge transistor having its channel connected between a VDD supply terminal and an output terminal, a functional network connected between the output terminal and a switch ground node, the network containing a plurality of transistors each having its gates connected to receive a respective one of a plurality of input signals and its channel connected together with those of the other transistors of the functional network in a configuration which provides the circuit with a predetermined logical function, and a ground switch transistor having its channel connected between the switch ground node and a VSS supply terminal. The gate of the ground switch transistor receives a clock signal which turns that transistor OFF during a precharge phase of the clock signal and ON during an active phase of the clock signal. The gate of the precharge transistor is connected to a precharge generator providing a voltage signal which biases that transistor to have a relatively high channel conductance during the precharge phase and biases that transistor to have a relatively low channel conductance during the active phase. The bias applied to the gate of the precharge transistor is such that the channel conductance of that transistor is sufficient to permit replenishment of charge at the output terminal lost from undesired leakage but not so high as to significantly increase the power dissipation of the circuit. Thus, the disclosed circuit provides stable output states which are characteristic of a static circuit while also having low power dissipation, high performance and low transistor count which are characteristic of a dynamic circuit.

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