Clustered logic arrays

Details Clustered logic arrays Clustered logic arrays

H - Electricity

03

K

328/146

H03K 19/20 (2006.01) H03K 19/177 (2006.01)

Patent

CA 1060959

CLUSTERED LOGIC ARRAYS ABSTRACT This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The out- put lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different func- tions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.

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