Cmos architecture for a digital radio receiver

Details Cmos architecture for a digital radio receiver Cmos architecture for a digital radio receiver

H - Electricity

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H01L 27/088 (2006.01) H01L 21/8234 (2006.01) H03D 7/12 (2006.01) H03F 3/19 (2006.01) H04B 1/16 (2006.01) H04B 1/18 (2006.01) H04B 1/26 (2006.01)

Patent

CA 2280128

A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in size and weight, without requiring performance to be compromised.

Un circuit intégré d'un émetteur-récepteur radio numérique comprend des transistors MOS avec des tensions de seuil normales dans les circuits numériques et avec des tensions de seuil diminuées au moins dans certains des composants analogiques H.F.. Ceci permet de diminuer la taille et le poids de l'émetteur-récepteur, sans porter atteinte à ses performances.

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