Cmos cell array with transistor isolation

Details Cmos cell array with transistor isolation Cmos cell array with transistor isolation

H - Electricity

03

K

328/127, 352/82.

H03K 19/088 (2006.01) H01L 21/765 (2006.01) H01L 27/02 (2006.01) H01L 27/118 (2006.01)

Patent

CA 1217828

- 13 - Abstract A new technique for forming CMOS custom logic circuits is disclosed wherein standard cells are used and the prior art technique of field oxide isolation is replaced with transistor isolation. That is, the boundaries between the cells are formed by transistors that are permanently "off", i.e., tied to the positive or negative voltage supply, depending on whether the transistors are p-channel or n-channel devices, respectively. Therefore, instead of having to deposit separate p+ and n+ source/drain diffusions for each cell, as in the prior art, a single p+ diffusion strip and a single n+ diffusion strip are utilized, where the polysilicon mask of both the logic and isolation transistors defines the cell sizes. Thus, the p+ and n+ diffusions become generic steps which do not vary from circuit to circuit, decreasing the turnaround time associated with custom logic circuit layout and design.

477132

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