Cmos integrated circuit fan-in logic tree layout arrangement

Details Cmos integrated circuit fan-in logic tree layout arrangement Cmos integrated circuit fan-in logic tree layout arrangement

H - Electricity

03

K

328/127

H03K 19/08 (2006.01) H03K 19/003 (2006.01) H03K 19/173 (2006.01) H04Q 3/52 (2006.01)

Patent

CA 1292044

Abstract A logic circuit, such as used in a crossbar digital switch, containing a multistage fan-in logic tree is arranged in a compact folded layout having a width equal to a single stage of the tree, in order to minimize wiring delays and signal skew.

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