Cmos integrated circuit having improved isolation

Details Cmos integrated circuit having improved isolation Cmos integrated circuit having improved isolation

H - Electricity

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H01L 21/76 (2006.01) H01L 21/762 (2006.01) H01L 21/82 (2006.01) H01L 21/8238 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1315419

Chen-Cochran-Leung 5-2-5 Abstract of the Disclosure A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide having a p-type channel stop region formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxideregion that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries. -8-

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