Cmos integrated circuit with high frequency power bus...

Details Cmos integrated circuit with high frequency power bus... Cmos integrated circuit with high frequency power bus...

G - Physics

11

C

356/133, 352/48,

G11C 11/40 (2006.01) H01L 27/10 (2006.01)

Patent

CA 1204511

CMOS INTEGRATED CIRCUIT WITH HIGH FREQUENCY POWER BUS ARRANGEMENT ABSTRACT OF THE DISCLOSURE A CMOS integrated circuit chip is designed to include a number of decoupling capacitors close to transistor cells in the chip so as to enable high frequency switching. The chip is formed on a substrate which includes a number of columns of wells of conductivity type opposite to that of the substrate. A number of columns of CMOS transistor pairs are formed in the substrate, with one transistor of each pair being formed in a well. Decoupling capacitance is provided by making power supply connections to the wells and substrate at a number of locations over the chip. These connections serve to reverse bias the well/substrate interface, thereby providing an associated capacitance which is located close to each transistor pair. The connections to the well and substrate are made by means of a grid metallization pattern which is connected to voltage and ground power buses which for a ring around the chip.

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