Cmos p-well selective implant method

Details Cmos p-well selective implant method Cmos p-well selective implant method

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H01L 21/265 (2006.01) H01L 21/033 (2006.01) H01L 21/266 (2006.01) H01L 21/762 (2006.01) H01L 21/8238 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1157574

CMOS P-WELL SELECTIVE IMPLANT METHOD Abstract of the Disclosure A method for fabricating a complementary metal- oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, marking the sub- strate to expose preselected areas for P-wells, ion implant- ing P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-well areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implanta- tion of P-type material may be accomplished in either a single stage or a two stage procedure.

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