H - Electricity – 04 – B
Patent
H - Electricity
04
B
H04B 1/16 (2006.01) H03K 19/0175 (2006.01) H03K 19/0185 (2006.01) H04B 10/06 (2006.01) H04L 25/02 (2006.01)
Patent
CA 2191634
A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.
nter the French Abstract here.
Pmc-Sierra Inc.
Pmc-Sierra Ltd.
Shapiro Cohen
LandOfFree
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