Cmos strobed comparator

Details Cmos strobed comparator Cmos strobed comparator

Category

H - Electricity

Subcategory

03

Subsubcategory

K

IPC codes

H03K 5/24 (2006.01) H03K 3/356 (2006.01)

Type

Patent

Patent number

CA 2084657

Description

An all CMOS voltage comparator circuit which incorporates a strobed latch. A strobe signal precharges the entire circuit to a known state which is independent of the input voltages and in which substantially no static current is drawn. Under static conditions after the circuit has been strobed, the source-coupled pair is virtually disconnected from the supply voltage(s) and draws almost no current, as well. then the circuit is strobed, a source-coupled FET pair amplifies the differential input signal, with positive feedback provided through a pair of cross-coupled PMOS load transistors, as well as cross-coupled NMOS cascode transistors. The source-coupled pair feeds a pair of output buffers, or drivers, whose FETs are sized such that a "low" voltage level is generated on both outputs until the source-coupled pair resolves the input voltage difference (i.e., the differential input voltage exceeds the switching threshold). At that time, the outputs become complementary digital levels and are usable.

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