Cmos technology high speed digital signal transceiver

Details Cmos technology high speed digital signal transceiver Cmos technology high speed digital signal transceiver

H - Electricity

03

M

H03M 9/00 (2006.01) H04L 7/033 (2006.01) H04L 27/227 (2006.01)

Patent

CA 2138106

CMOS technology high speed digital signal transceiver, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged. Fig. 4.

L'invention est un émetteur-récepteur de signaux numériques à grand débit à technologie CMOS dans lequel le récepteur est doté d'un circuit d'extraction de signaux d'horloge à alignement automatique sur les données incidentes sans verrouillages parasites. Utilisant une boucle à asservissement de phase, ce circuit produit un signal d'horloge asservi au signal incident à l'aide d'un oscillateur local commandé en tension par deux boucles de rétroaction, une boucle principale pour les corrections de fréquence et de phase, et une boucle secondaire pour les corrections de phase. Des circuits de types nouveaux pour les détecteurs de phase et les filtres passe-bas sont également décrits. (Figure 4).

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