Cmos to ecl interface circuit

Details Cmos to ecl interface circuit Cmos to ecl interface circuit

H - Electricity

03

K

328/128

H03K 19/094 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 1262175

CMOS TO ECL INTERFACE CIRCUIT Abstract of the Disclosure The circuits of the present invention convert CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS and ECL circuits. One preferred circuit embodiment is comprised of three p- channel transistors and one n-channel transistor. The first p-transistor has its source connected to a reference potential, such as ground, and its drain electrode connected to the source of the second p- transistor. The drain and the gate of the second p- transistor are connected together to an output termi- nal. The drain of the third p-transistor is connected to the output terminal. The gate and the source of the third p-transistor are connected to the drain of the n-transistor. The source of the n-transistor is connected to a CMOS compatible potential source. The CMOS logic level signal is coupled to the gate of the first p-transistor and the gate of the n-transistor. The output terminal is connected to an ECL compatible potential source via a termination resistor. Two other circuit embodiments are disclosed which provide for non-inverted and inverted outputs.

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