Column redundancy in semiconductor memories

Details Column redundancy in semiconductor memories Column redundancy in semiconductor memories

G - Physics

11

C

G11C 11/408 (2006.01) G11C 29/00 (2006.01)

Patent

CA 2202692

This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for energizing appropriate memory elements in response to the decoder memory addresses received at an input thereof; redundant column drivers; and switch means for selectively connecting the redundant column driver into a selected normal driver path.

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