Combined scrambler-encoder for multilevel digital data

Details Combined scrambler-encoder for multilevel digital data Combined scrambler-encoder for multilevel digital data

H - Electricity

04

K

354/106, 340/70

H04K 1/04 (2006.01) H03M 5/00 (2006.01) H04L 9/00 (2006.01) H04L 25/49 (2006.01)

Patent

CA 1049414

COMBINED SCRAMBLER-ENCODER FOR MULTILEVEL DIGITAL DATA Abstract of the Disclosure A high-speed digital data transmission system combines quadrature amplitude modulation with scrambling-descrambling, differential amplitude coding-decoding, and Gray-to- rotational coding-decoding of multilevel data symbols channeled at baseband, i.e., including frequencies extending down to zero, onto parallel bit streams with a minimization of error multiplication. Scrambling and descrambling facilitate timing recovery and equalizer adjustment. Differential and rotational encoding and decoding compensate for phase ambiguities in the signal constellation, i.e., points on a space diagram representative of the tips of multilevel symbol vectors.

226119

Affiliated with

Also associated with

Rating

Combined scrambler-encoder for multilevel digital data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Combined scrambler-encoder for multilevel digital data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combined scrambler-encoder for multilevel digital data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-394055