H - Electricity – 04 – L
Patent
H - Electricity
04
L
340/70
H04L 9/00 (2006.01) H04L 25/03 (2006.01)
Patent
CA 1170330
ABSTRACT In a communication system containing a scheme for externally synchconizing and scrambling digital data signals, serial digital data signals to be transmitted are subdivided into prescribed numbers or sets between which additional or overhead bits are inserted, the resulting sequence being summed in a modulo-two adder with a multi-bit maximal length PN sequence so that one of the overhead bits is one of the bits of the maximal length scrambling sequence. To mark the beginning of a frame of data, one of the possible code states of the multi-bit sequence is selected. The multiplexing operation is such that the data rate is increased by a prescribed factor relative to the original data rate to provide for the insertions of the overhead bits without loss of data. The resulting higher data rate sequence is then modulo-two added with the output of a scrambler and transmitted. The resulting scrambled data sequence contains the multi-bit bit PN framing sequence inserted in sync bit positions exactly where required. Advantageously, with this scrambling technique, since each unique state of the framing se corresponds to only one state of the scrambling sequence, the receiver station can proceed to descramble the received scrambled sequence by observing the state of the received framing sequence. In order to recover the framing sequence and descramble the data at the receiver station, the incoming scrambled data -48- sequence is initially applied to timing recovery circuitry which derives a clock signal synchronized with the received data signal and bit-synchronizes the data and the clock. Frame synchronization is begun by loading a plurality of received scrambled data bits at preselected intervals into a shift register that forms pact of a local framing sequence generator. This shift register is clocked at a prescribed fraction of the frequency of the clock derived from the received data sequence. If the clock is in phase with the bit positions of the framing sequence, the shift register will be loaded with successive bits of the framing sequence and the local framing sequence generator will therefore be capable of generating a PN sequence identical to and in phase with the transmitted framing sequence. If the chosen sequence of bits does not belong to the framing sequence, the output of the scrambling sequence generator will be out of phase with the framing sequence. When this occurs the clocking of the shift register is inhibited by one pulse and the incoming data stream is effectively caused to be shifted or displaced by one bit position, and the above process is repeated as necessary until eventually the framing sequence is located and the local framing sequence generator is in phase with the framing sequence. At this time, the stages of a separate shift register, which forms part of a descrambled PN sequence generator, are forced to the state coincident with the frame marker. This separate shift register is clocked at the incoming data rate by the recovered clock and is output is modulo-two added with the incoming digital data stream, thereby -49- recovering the original multiplexed data with the original zeros inserted at the framing bit positions. To recover the original data stream, the descrambled sequence is applied to a demultiplexer which effectively deletes every overhead bit and outputs the original data at the original data rate. -50-
376415
Halpern Peter H.
Patisaul Charles R.
Toy James W.
Harris Corporation
Shapiro Cohen
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