Common bus communication system with reduced interface memories

Details Common bus communication system with reduced interface memories Common bus communication system with reduced interface memories

H - Electricity

04

L

H04L 12/56 (2006.01) H04L 29/06 (2006.01)

Patent

CA 2052364

In a common bus communication system in which multiple bus interfaces (2) are connected to the common bus, each bus interface comprises a main memory (21) and an auxiliary memory (28, 29). When a packet destined to the own interface is detected by an address detector (22), memory control data is stored into the auxiliary memory in a location corresponding to a destination user terminal (5;) as well as to the location of the packet in the main memory. When a read request is received from the destination user terminal, control data is fetched from the auxiliary memory and a packet in the data memory is accessed according to the fetched control data, and a copy of the accessed packet is sent to the destination user terminal and following the transmission the control data is updated. Packets propagating along the common bus are stored into the main memory according to the updated control data.

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