Communication controller using multiported random access memory

Details Communication controller using multiported random access memory Communication controller using multiported random access memory

G - Physics

06

F

354/234

G06F 13/12 (2006.01) G06F 13/18 (2006.01) G06F 13/36 (2006.01) G06F 13/40 (2006.01) G06F 15/173 (2006.01)

Patent

CA 1241766

ABSTRACT A communication controller for facilitating bidirectional digital data transfers between a host processor and various types of networks, The controller architecture is characterized by multiple independent data transfer buses coupled to a central multiple port random access memory. The architecture avoids microprocessor bus contention in favor of RAM contention and thus enhances aggregate system thoughput. Moreover, the buses are capable of performing operations concurrently to thereby further enhance system throughput.

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