Compact sram cell layout

Details Compact sram cell layout Compact sram cell layout

G - Physics

11

C

G11C 11/40 (2006.01) H01L 21/8244 (2006.01) H01L 23/532 (2006.01) H01L 27/11 (2006.01)

Patent

CA 2047329

ABSTRACT OF THE DISCLOSURE A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates (30a, 30b) substantially parallel to each other. One interconnect (45) connects the gate (30b) of one transistor to an electrode (35a) of the other transistor. Another interconnect (463 connects the gate (30a) of the other transistor to an electrode (35b) of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circuit line (47) is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer. Also, in an array of memory cells, some circuit lines (37) are formed in the substrate, and other circuit lines (47) are formed directly above those in-the- substrate lines (37). The in-the-substrate lines (37) are provided with extensions (42a, 42b) that permit to contact these lines (37) without contacting the other, overlying lines (47).

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