Compensating for differences between clock signals

Details Compensating for differences between clock signals Compensating for differences between clock signals

H - Electricity

03

L

H03L 7/00 (2006.01) H03L 7/06 (2006.01) H04L 7/00 (2006.01)

Patent

CA 2457499

A clock compensation circuit (102) is provided. The circuit comprises a clock synchronization circuit (110) coupled to receive an input clock signal (101- 1), wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals (105). The circuit further comprises a phase comparator (120s) coupled to receive one of the plurality of internal logic clock signals and a sample clock (PHYRET) from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel (115s) coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.

L'invention concerne un circuit de compensation d'horloge (102) qui comprend un circuit de synchronisation d'horloge (110) couplé pour recevoir un signal d'horloge d'entrée (101-1), ce circuit de synchronisation d'horloge émettant un signal d'horloge maître ainsi qu'une pluralité de signaux d'horloge logique interne (105) ; un comparateur de phases (120) couplé pour recevoir un de ces signaux d'horloge logique interne ainsi qu'une horloge d'échantillonnage (PHYRET) d'un récepteur connexe, ce comparateur de phase émettant un signal de commande sur la base d'une comparaison de phases entre l'horloge d'échantillonnage et un desdits signaux d'horloge logique interne ; et enfin, un canal de convertisseur abaisseur (115) couplé pour recevoir chacun desdits signaux d'horloge logique interne et le signal de commande, ainsi que pour transmettre les données en phase avec l'horloge d'échantillonnage en faisant intervenir le signal d'horloge logique interne sur la base du signal de commande.

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