Complementary enhancement mode mos transistor structure with...

H - Electricity – 01 – L

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

356/125

H01L 21/18 (2006.01)

Patent

CA 1058328

COMPLEMENTARY ENHANCEMENT MODE MOS TRANSISTOR STRUCTURE WITH SILICON GATE Abstract of the Disclosure A p+ doped silicon gate metal oxide comple- mentary transistor structure fabricated on a p-type substrate of semiconductor material with an insulating layer of silicon dioxide on the surface of the substrate and an outer layer of glass disposed over the insulating layer, An intermediate layer of electrically conductive p+ doped polycrystalline silicon is disposed between the layers of silicon dioxide and glass, This layer forms the silicon gate for enhancement mode complementary MOS transistors.

201526

LandOfFree

Say what you really think

Search LandOfFree.com for Canadian inventors and patents. Rate them and share your experience with other people.

Rating

Complementary enhancement mode mos transistor structure with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Complementary enhancement mode mos transistor structure with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary enhancement mode mos transistor structure with... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFCA-PAI-O-207861

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.