H - Electricity – 03 – K
Patent
H - Electricity
03
K
328/128
H03K 19/094 (2006.01) H03K 19/017 (2006.01) H03K 19/0175 (2006.01) H03K 19/0944 (2006.01)
Patent
CA 1188755
ABSTRACT OF THE DISCLOSURE A complementary MOSFET logic circuit has a complementary MOS inverter with a predetermined ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and predetermined threshold voltages of the FETs so as to have an input voltage characteristic adapted to a desired output voltage characteristic, and a buffer circuit arranged so that a bipolar transistor, which receives at its base a signal from the output terminal of the comple- mentary MOS inverter, and an N channel MOSFET, which receives at its gate the input signal applied to the comp- lementary MOS inverter, are connected in series between supply potentials, whereby an output signal corresponding to a logic output signal of the complementary MOS inverter is produced at the series connection point of the bipolar transistor and the MOSFET in the buffer.
396984
Matsuo Kenji
Suzuki Yasoji
Ridout & Maybee Llp
Tokyo Shibaura Denki Kabushiki Kaisha
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