Computationally efficient modular multiplication method and...

Details Computationally efficient modular multiplication method and... Computationally efficient modular multiplication method and...

G - Physics

06

F

G06F 7/44 (2006.01) G06F 7/52 (2006.01) G06F 7/72 (2006.01)

Patent

CA 2251178

A computationally efficient multiplication method and apparatus for modular exponentiation. The apparatus uses a preload register, coupled to a multiplier at a second input port via a KN bit bus to load the value of the "a" multiplicand in the multiplier in a single clock pulse. The "b" multiplicand (which is also KN bits long) is supplied to the multiplier N bits at a time from a memory output port via an N bit bus coupled to a multiplier first input port. The multiplier multiplies the N bits of the "b" multiplicand by the KN bits of the "a" multiplicand and provides that product at a multiplier output N bits at a time, where it can be supplied to the memory via a memory input port.

Affiliated with

Also associated with

Rating

Computationally efficient modular multiplication method and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computationally efficient modular multiplication method and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computationally efficient modular multiplication method and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-2038959