Computer interconnect coupler employing crossbar switching

Details Computer interconnect coupler employing crossbar switching Computer interconnect coupler employing crossbar switching

G - Physics

06

F

354/233

G06F 13/40 (2006.01) G06F 11/16 (2006.01) G06F 11/20 (2006.01) G06F 11/22 (2006.01) G06F 15/16 (2006.01)

Patent

CA 1312677

COMPUTER INTERCONNECT COUPLER EMPLOYING CROSSBAR SWITCHING ABSTACT A computer interconnect coupler has a set of junctors which are assigned to channel transmitters and channel receivers for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment code responsive to the incoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added and a hierarchical rotating priority scheme enables the additional channels to have equal priority with the previously existing channels without requiring reprogramming. Moreover, the processing and queueing of routing requests is made more effective by grouping the requests into different priority levels and using separate but duplicate arbitration logic to resolve simultaneous requests within the same priority group. The coupler also includes a plurality of timers which determine fault conditions, and a diagnostic processor monitors the timers and associated error flags to diagnose faults to the board level. The conditions existing at the time of fault diagnosis are written into a non-volatile memory located on the circuit board. Therefore, the information is physically carried along with the board to the repair facility.

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