Computer look-ahead instruction issue control

Details Computer look-ahead instruction issue control Computer look-ahead instruction issue control

G - Physics

06

F

354/230.71

G06F 9/38 (2006.01) G06F 15/78 (2006.01)

Patent

CA 1321029

ABSTRACT A system for scheduling instruction issuance in a vector register computer achieves increased efficiency of operation by performing pre-issuance checks to determine if resources requested by the instruction will be available when the instruction issues. A decoding apparatus first determines particular resources requested by the instruction, which includes apparatus for decoding vector register requests, functional unit requests, and address and scalar register path requests. Following decoding, a conflict resolution apparatus checks resource reservation flags to determine if the requested resources will be available when the instruction issues. If any requested resources will be busy, the system issues a primary conflict signal. At the scheduled instruction issuance time, the system again checks the resource reservation flags in response to the primary conflict signal. If the requested resources are still busy, the system generates a secondary conflict signal for as long as the requested resources remain busy. Finally, when the instruction issues, the system sets the resource reservation flags to reserve the requested resources for the instruction.

605015

Affiliated with

Also associated with

Rating

Computer look-ahead instruction issue control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer look-ahead instruction issue control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer look-ahead instruction issue control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1250124