Computer memory apparatus

Details Computer memory apparatus Computer memory apparatus

G - Physics

06

F

354/237

G06F 12/04 (2006.01) G11C 5/00 (2006.01) G11C 8/12 (2006.01) G11C 8/18 (2006.01)

Patent

CA 1262492

ABSTRACT OF THE DISCLOSURE A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of random access memory (RAM) chips arranged in one of two subsystem configurations and mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. The configurations correspond to a common stack arrangement which provides double the normal amount of density and an adjacent stack arrangement of normal density. As a function of an input density signal, chip select circuits preselect a pair of blocks of RAM chips from a common stack or pair of adjacent stacks. Timing circuits generate a plurality of column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the read out of a pair of words from the preselected blocks of a single stack or adjacent stacks in tandem into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out into the data registers in the same sequence providing a double fetch capability without any loss in performance.

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