Computer memory array control

Details Computer memory array control Computer memory array control

G - Physics

06

F

G06F 3/06 (2006.01) G06F 11/10 (2006.01) G06F 12/08 (2006.01) G11B 20/10 (2006.01) G11B 20/18 (2006.01)

Patent

CA 2127380

2127380 9314455 PCTABS00024 A computer memory controller for interfacing to a host computer comprises a buffer memory (26) for interfacing to a plurality of memory units (42) and for holding data read thereto and therefrom. A central controller (22) operative to control the transfer of data to and from the host computer and the memory units (42). The buffer memory (26) is controlled to form a plurality of buffer segments for addressably storing data read from or written to the memory units (42). The central controller (22) is operative to allocate a buffer segment for a read or write request from the host computer, of a size sufficient for the data. The central controller (22) is also operative in response to data requests from the host computer to control the memory units (42) to seek data stored in different memory units (42) simultaneously.

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