Computer memory interface apparatus

Details Computer memory interface apparatus Computer memory interface apparatus

G - Physics

06

F

354/241

G06F 13/00 (2006.01) G06F 13/42 (2006.01) G11C 11/4076 (2006.01) G11C 11/408 (2006.01)

Patent

CA 1087753

ABSTRACT Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS (column address strobe) signal is generated in response to an RAS (row address signal) signal via a device which tracks the worst case delay of memory address signals and does not permit the application of the CAS signal to memory until the worst case delay of the memory address signals has been accounted for. -1-

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