Computer system high speed link method and link and means

Details Computer system high speed link method and link and means Computer system high speed link method and link and means

G - Physics

06

F

354/233

G06F 13/00 (2006.01) G06F 13/42 (2006.01)

Patent

CA 2015214

This embodiment provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High Performance Parallel interface (HPPI) standard on processors complexes like the IBM? 3090TM having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

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