G - Physics – 06 – F
Patent
G - Physics
06
F
340/89
G06F 15/16 (2006.01) G06F 13/18 (2006.01)
Patent
CA 1104226
ABSTRACT OF THE DISCLOSURE A computer useful as a data network communications processor unit is shown having multiple processors and a common set of independent memory resources accessed by all of the processors over a common bus, and controlled by a common clock. Logic circuitry for allocating the pro- cessors to the individual memory resources is formed by a set of individual contention logic circuits, one associated with each processor, all capable of operating in parallel time, being combinatoric in nature and requiring no sequential states of operation, or logic signals sequentially propagated through the set of logic circuits, and together enabling one allocation per clock interval. The individual contention circuit for each processor features input from each independent memory resource denoting its availa- bility, interconnection with the other contention circuits to provide the longest length of time any other processor of the set has waited for access, priority interconnection with the other contention circuits ranking the circuits according to a pre-determined priority rule to break ties between the circuits in case of equality of all other criteria, and connection with its respective processor indicating need of the processor for access over the bus and the identity of the memory resource required by the processor. Each contention circuit compares its length of time of waiting for the address/data bus to that of the other circuits and connects its own pro- cessor automatically to the bus when its inputs and connections establish for it that: (a) it requires access to a memory resource, (b) and the memory resource it requires is available, (c) and it has waited as long or longer than any other processor, (d) and there is no processor with higher rank meeting conditions (a) through (c).
286217
Codex Corporation
Smart & Biggar
LandOfFree
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