Computer with expanded addressing capability

Details Computer with expanded addressing capability Computer with expanded addressing capability

G - Physics

11

C

354/237, 354/239

G11C 7/00 (2006.01) G06F 12/06 (2006.01) G06F 13/00 (2006.01)

Patent

CA 1181178

COMPUTER WITH EXPANDED ADDRESSING CAPABILITY Abstract A computer system has an addressing capability many times greater than the number of addresses which can be generated by its binary address lines through the use of a plurality of addressable banks (14, 16, 18, 22, 30, 34) (memory, addressable peripherals or addressable system controls) in each of a plurality of different ranges, (II, III, IV) with several different banks in each of said plural address ranges being useable in combination for any given mode of operation or program. Bank selection within any address range is effected within program control by first supplying (1) an address which enables a bank select decoding latch (28), and (2) a data code for selecting the desired bank, whereupon the bank will be latched and en- abled for use in a later normal addressing operation. ROM banks (14, 16, 18), implemented in monolithic circuit form, are selected by decoder latch outputs (D2, D1, D0) which cause the bank (40) to be energized from a non-energized state, thereby eliminating (13 the need for a separate chip-select terminal, and (2) standby power consumption. Addressable peripheral equipment and system controls (30, 34) (non-ROM hardware) are mapped in an address range (III) containing ROM banks. Writing to this address range auto- matically goes to the non-ROM hardware since the ROM banks are incapable of receiving data. Reading from the non-ROM hardware is effected by preselecting non-ROM hardware through the use of specific data codes.

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