Configuration control in a programmable logic device using...

Details Configuration control in a programmable logic device using... Configuration control in a programmable logic device using...

G - Physics

05

B

G05B 19/045 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2295445

A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches (151) within a Configuration Register (150). The Configuration Register (150) is included within the JTAG structure as a Test Data Register (TDR) (180). Each configuration bit within the Configuration Register (150) consists of a Configuration Latch (151), and each configuration latch (151) has an output used as a configuration control signal (160) within an output logic macrocell. The configuration register's input signal (149) is selectively provided from either a set of serially connected configuration bit non-volatile element sense latches (120) or from the JTAG Test Data In (TDI) data pin (101) for configuration, prototyping, and testing.

Une interface de circuit d'essai périphérique (JTAG) est utilisée pour la production de données pour un ensemble de verrous de configuration (151) au sein d'un registre de configuration (150). Le registre de configuration (150) est inclus dans la structure JTAG sous forme de registre de données d'essai (TDR) (180). Chaque bit de configuration (150) consiste en un verrou de configuration (151) et chaque verrou de configuration (151) produit un signal de sortie utilisé comme un signal de commande de configuration (160) au sein d'une macrocellule logique de sortie. Le signal d'entrée (149) du registre de configuration est produit sélectivement par un ensemble de verrous de détection d'élément rémanent à bits de configuration connectés en série (120) ou par la broche de données (101) formant entrée de données d'essai JTAG, pour la configuration, le prototypage et l'essai.

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