Consecutive identical digit suppression system in a digital...

Details Consecutive identical digit suppression system in a digital... Consecutive identical digit suppression system in a digital...

H - Electricity

04

L

325/1, 340/72

H04L 25/49 (2006.01)

Patent

CA 1186763

TITLE OF THE INVENTION Consecutive Identical Digit Suppression System in a Digital Communication System ABSTRACT OF THE DISCLOSURE An encoder for suppression of a consecutive identical digit in a digital transmission system facilitates the reproduc- tion of a clock signal for regenerating reception data, and keeping the average signal level constant. According to the present invention, a single bit (x) is inserted for every pre- determined number (m) of input digits, and said insertion bit is a complement of the sign of the previous k bits where k is an integer satisfying 1?k?m. Preferably, the value k is 1. The present invention is useful for digital communications higher than 100 Mbits/second, in particular, in optical communications.

401079

Affiliated with

Also associated with

Rating

Consecutive identical digit suppression system in a digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Consecutive identical digit suppression system in a digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Consecutive identical digit suppression system in a digital... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1202505