Contact configuration for semiconductor processing

Details Contact configuration for semiconductor processing Contact configuration for semiconductor processing

H - Electricity

01

L

356/136

H01L 21/28 (2006.01) H01L 21/033 (2006.01) H01L 21/336 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1076266

Abstract of the Disclosure A method of forming contact apertures through a plurality of layers of insulating material sequentially formed on a semi-conductor wafer utilizing a two contact mask operation wherein the apertures in the first contact mask for providing an opening to the field oxide are aligned with and are larger than, the apertures in the second contact mask. A first etch resistant mask with apertures aligned with contact regions is formed on the wafer. Subsequently there is formed on the wafer a second etch resistant mask with apertures smaller in size than the apertures of the first mask.

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