Control of cache buffer for memory subsystem

Details Control of cache buffer for memory subsystem Control of cache buffer for memory subsystem

G - Physics

06

F

354/241, 354/246

G06F 12/00 (2006.01) G06F 12/08 (2006.01) G11B 5/012 (2006.01) G11B 20/18 (2006.01)

Patent

CA 1212780

Abstract of the Disclosure A solid-state cache memory subsystem configured to be used in conjunction with disk drives for prestaging of data in advance of its being called for by a host computer is dis- closed, featuring means for establishing and maintaining precise correspondence between storage locations in the solid-state array and on the disk memory, for use in establishing a reoriented position on a disk in the event of error detection, and in order to determine when a predetermined quantity of data has been read from the disk into the cache in a staging operation.

441190

Affiliated with

Also associated with

Rating

Control of cache buffer for memory subsystem does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control of cache buffer for memory subsystem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control of cache buffer for memory subsystem will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1308214