Controlled delay circuit

Details Controlled delay circuit Controlled delay circuit

H - Electricity

03

K

H03K 5/13 (2006.01) H03K 5/04 (2006.01) H03K 5/151 (2006.01)

Patent

CA 2110247

COMPANY NAMED: TEXAS INSTRUMENTS FRANCE Controlled delay circuit. ABSTRACT Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source o two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, Sl, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit. Fig. 3

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