Controlled delay digital clock signal generator

Details Controlled delay digital clock signal generator Controlled delay digital clock signal generator

H - Electricity

03

K

H03K 3/86 (2006.01) H03K 4/00 (2006.01) H03K 5/15 (2006.01)

Patent

CA 2111054

1 ABSTRACT Controlled Delay Digital Clock Signal Generator SUMMARY OF TECHNICAL CONTENT OF THE INVENTION Controlled delay digital clock signal generator, characterized in that it comprises means (I5, I6, I7, I8, I9, II0, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and it complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NOO, AO, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) achieving the logic combinations of the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes. Fig. 1.

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