Correlated sliver latch

Details Correlated sliver latch Correlated sliver latch

H - Electricity

03

K

328/127, 328/150

H03K 19/00 (2006.01) H03K 3/037 (2006.01)

Patent

CA 2017707

Abstract A VSLI circuit includes a plurality of state device circuits on a VLSI chip. Each of the state device circuits includes a latch and is clocked by a pulse generator circuit which produces narrow pulses that are coupled to the clock input of the latch. The narrow pulses have a pulse width substantially equivalent to the propagation delay through the latch of the state device circuits. By taking advantage of the high correlative percentages of devices on portions of the chip, master-slave flip flops can be implemented using only a single latch with a pulse generator.

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