G - Physics – 06 – F
Patent
G - Physics
06
F
354/105, 354/236
G06F 3/00 (2006.01) G06F 13/12 (2006.01) G06F 13/38 (2006.01) H04L 25/45 (2006.01)
Patent
CA 1065061
CPU - I/O BUS INTERFACE FOR A DATA PROCESSING SYSTEM ABSTRACT OF THE DISCLOSURE There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device transceiver apparatus. The device trans- ceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU trans- ceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/ controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data trans- mission means which maintains accurate processing of data regard- less of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology. -1-
270520
LandOfFree
Cpu-1/0 bus interface for a data processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cpu-1/0 bus interface for a data processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cpu-1/0 bus interface for a data processing system will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-14880