Cryptography processor and method with optional status...

H - Electricity – 04 – L

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H04L 9/00 (2006.01) H04L 29/02 (2006.01)

Patent

CA 2044860

68061-102 PIPELINED CRYPTOGRAPHY PROCESSOR AND METHOD FOR ITS USE IN COMMUNICATION NETWORKS ABSTRACT OF THE DISCLOSURE Cryptographic apparatus, and a related method for its operation, for in-line encryption and decryp- tion of data packets transmitted in a communication network. A full-duplex cryptographic processor is posi- tioned between two in-line processing entities of a net- work architecture. For example, in a fiber distributed data interface (FDDI) network, the processor is posi- tioned between a media access control (MAC) sublayer and a ring memory controller (RMC). Incoming informa- tion packets are analyzed to decide whether or not they contain encrypted data and, if they do, are subject to decryption before forwarding. Outbound information pac- kets have their data portions encrypted if called for, and are usually forwarded toward the network communica- tion medium. Cryptographic processing in both direc- tions is performed in real time as each packet is streamed through the processor. The processing of out- bound information packets includes using optional data paths for looping of the processed information back in a reverse direction, to permit the host system to per- form local encryption or decryption for various pur- poses.

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